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Ex parte LOO et al. - Page 4
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Board of Patent Appeals and Interferences > 1997 > Ex parte LOO et al. - Page 4
Appeal No. 95-4714
Application No. 08/046,476
Beginning with the preamble, the claimed "computer
workstation" reads on the elements shown in Figure 1, which
includes the claimed central processor (CPU 11), which generates
a virtual address of A bits in size which uniquely identifies
bytes of instructions or data within a given virtual context
(Spec. at 5, lines 13-15). The operating system, which is common
to all processes or contexts, lies within a common region at the
top of the 2 bytes virtual address space for each contextA
(Spec. at 10, lines 1-16). The specification indicates (at 1,
lines 2-5) that the operating system is "multi-user" and has
"multiple concurrently active contexts," as required by the
claim. The claim's recitation that the operating system "ha[s] a
kernel wherein virtual addresses are assigned for each of a
plurality of users" finds support in the paragraph bridging pages
17 and 18. As also required by the preamble, the workstation has
a cache data array (19), which includes a plurality of cache
blocks, each having a virtual cache block address and an
associated block tag (which is stored in cache tag array 23).
Although not required by the claim, we note that context register
32 contains C virtual address bits which identify the currently
running context or process (Spec. at 10, lines 1-3).
The paragraph that begins "flush control logic means" reads
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Last modified: November 3, 2007
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