Court Opinions
State Laws
|
Ex parte LOO et al. - Page 10
Legal Research Home >
Board of Patent Appeals and Interferences > 1997 > Ex parte LOO et al. - Page 10
Appeal No. 95-4714
Application No. 08/046,476
(Fig. 1) which includes a number of processing elements (100,
105, 110) which are connected to a plurality of main system
memory elements (165, 170, 175, 186) via processor buses (115,
116), master interfaces (120, 125), system buses (130, 131),
slave interfaces (135, 140, 145, 150), and memory buses (155,
156, 160, 161). As shown in Figure 2, each processing element
contains a microprocessor unit (MPU) 210, a cache memory 250 of
the non-write through type (col. 8, lines 4-5), a block status
memory 255, a memory management unit (MMU) 200, an internal
sequence controller 240, and an external control sequencer 245.
The MPU is "a conventional data processing device capable of
executing both user application programs and supervisor programs
which control and coordinate the operation of the associated
processor" (col. 4, lines 8-12). Accordingly, the cache memory
contains fixed supervisor code and data, overlayable supervisory
code and data, and user code and data (see Fig. 5). We agree
with the examiner that one of Stiffler's processing elements
(e.g., 100) can be considered to be a "computer workstation" in
the sense of claim 13.
Claim 13 additionally requires that the operating system be
of the "multi-user" type and "have multiple concurrently active
contexts." The examiner contends (Answer at secs. 9b and 11d),
- 10 -
Page: 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
Last modified: November 3, 2007
|
|
