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Ex parte LOO et al. - Page 11
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Board of Patent Appeals and Interferences > 1997 > Ex parte LOO et al. - Page 11
Appeal No. 95-4714
Application No. 08/046,476
and we agree, that it would have been obvious to have a plurality
of different users operate a plurality of Stiffler's workstations
(i.e., processing elements) at the same time. Even though each
workstation runs only one context at a time (see col. 9, lines
27-31), the result will be a multi-user operating system that
concurrently runs plural contexts.
The preamble's requirement that the operating system have a
“kernel wherein virtual addresses are assigned for each of a
plurality of users” also appears to be satisfied by Stiffler’s
operating system, which causes the MPU (210) in each processing
element to produce a 16 megabyte range of virtual addresses
between 000000 and FFFFFF virtual addresses within a specified
range (col. 7, lines 3-8; see Figs. 5 and 6). The remaining
preamble limitations are also satisfied as follows: the claimed
cache data array (250 in Fig. 2) includes a plurality of cache
blocks each having a cache block address and an associated cache
block tag (which is stored in block status memory 255 in Fig. 2).
The foregoing elements have different reference numerals in
the detailed workstation block diagram formed by Figures 7
(sheets 1 and 2) and 8. The central processor is MPU 702, the
cache data array is cache RAM 738, and the block status memory is
labeled 736. These figures also depict the elements of
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Last modified: November 3, 2007
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