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Ex parte LOO et al. - Page 15
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Board of Patent Appeals and Interferences > 1997 > Ex parte LOO et al. - Page 15
Appeal No. 95-4714
Application No. 08/046,476
with a shared, multi-user operating system having
multiple concurrently active contexts and a kernel;
main memory;
a memory management unit, coupled to said
processor and said main memory, for translating an
address in virtual space into a corresponding address
in physical space;
a virtual cache data array, coupled to said
central processing unit, for storing a first plurality
of blocks of data;
a virtual cache tag array, coupled to said virtual
cache data array and said central processing unit, for
storing a plurality of tag array elements wherein, each
tag array element corresponds to a particular block of
data stored in said virtual cache data array and
further includes: a validity bit, a modification bit, a
protection bit, a write allowed bit, a plurality of
virtual address field bits, and a plurality of context
bits;
cache hit logic means, coupled to said processor
and said virtual cache tag array, for determining
whether accesses from said central processing unit
result in a cache hit or a cache miss;
cache flush logic means, coupled to said central
processing unit and said cache hit logic means, for
directing the flushing of said virtual cache data
array;
wherein said central processing unit includes
means, disposed within the kernel of said shared,
multi-user operating system, for coupling a context
match flush command comprising a plurality of context
identifier bits, to said cache flush logic means and
said virtual cache tag array, such that in response to
said context match flush command, said cache flush
logic means flushes a first block of data from said
virtual cache data array in the event that:
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