Appeal No. 94-4061
Application 07/659,683
As to claim 6, the examiner states that it is not clear
what role the recirculating shift register means has within the
scheme of the invention.
Appellant's specification discloses that the shift
register 28 is initially loaded by initializing circuit 46 with a
logic pattern 1,0,0,0 so that the output of latches 44.1, 44.2,
44.3 and 44.4 depicted in Figure 1 are set at 1,0,0,0 (Specifi-
cation, page 8). The respective outputs of the latches 44.1 to
44.4 are connected to one input of one of AND gates 30.1, 30.2,
30.3 and 30.4. The other input of the AND gates is connected to
the output lines L1, L2, L3, and L4 from address decoder 16.
(Specification, page 8, Figure 1). The specification also
teaches that if the logic pattern on L1, L2, L3, L4 is 1,0,0,0:
the outputs of the AND-gates 30.1 to 30.4 go to
levels 1,0,0 and 0, respectively (since both
inputs of the gate 30.1 are at level 1, whereas
the two inputs of each of the gates 30.2 to 30.4
are at level 0). Consequently, the output of the
OR-gate 32 goes active (goes to level 1) and the
counter 26 is reset to zero. [Specification,
page 9]
The specification also discloses that if the logic pattern on
lines L1, L2, L3 and L4 does not match the logic pattern output
from latches 44.1, 44.2, 44.3 and 44.4:
the mismatch between the bit pattern on
the lines L1 to L4 and the pattern
outputted by the shift register will
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Last modified: November 3, 2007