Appeal No. 94-4061
Application 07/659,683
instruction execution in Proto is an
alternate design to the means of
checking valid sequence of instruction
execution in Gercekci and the person
would have implemented either means as
an equivalent option depending on the
inter-facing constraints imposed by
other means of the system. [Examiner's
Answer, Page 6]
As the watchdog instruction decoder is recited in claim
9 in means-plus-function format, we must look to the
specification and construe the "means" language so as to be
limited to the corresponding structure disclosed in the
specification and equivalents thereof. In re Donaldson 16 F.3d
1189, 1195, 29 USPQ2d 1845, 1850 (Fed. Cir. 1994).
Appellant's disclosed watchdog instruction decoder
means is an address decoder 16 which receives an address portion
of each instruction executed in memory and activates one of lines
L1, L2, L3, L4 in response to detecting an address of a watchdog
instruction. Proto discloses no such address decoder. Even if
we accept the examiner's rationale that the decoder in Proto is
within memory device (11) (Examiner's Answer, page 10), there is
no disclosure of an address decoder as disclosed in the
specification or an equivalent thereof. In view of the
foregoing, we will not sustain the examiner's rejections of
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