Appeal No. 96-0033
Application 08/066,638
Representative independent claim 1 is reproduced below:
1. A circuit for controlling data transfers between a first
device (1) and a second device (2) which operate at different
data rates, the first device providing data on an output bus at a
first rate together with strobe signals indicating data is
available to be transferred, the second device receiving data at
a second rate which is the rate of clock signals provided by the
second device, comprising:
at least R buffer registers (10, 12; 210) for receiving data
from the first device, R being an integer number equal to T+(T-1)
x (B-1), where T is a maximum number of data entities that can be
provided by the first device in a period of a clock signal and B
is a number of consecutive periods during which the first device
can provide a maximum number of data entities,
counting means (28;222) for generating R x (R+1) distinct
values in response to the strobe signals applied thereto;
decoding means coupled to the counting means, for generating
signals representative of the values generated by the counting
means and active loading signals used to cause the data from
the first device that are available at each strobe signal to be
loaded in a register selected among the buffer registers (R1 to
Rr) in a fixed sequence;
gating means (16, 20, 216), coupled to the buffer registers,
for selectively gating the data from the first device into the
buffer registers in response to said active loading signals;
storing means (44) responsive to the strobe signals, the
clock signals provided by the second device and the signals
representative of the values generated by the counting means,
for keeping track of those buffer registers which contain data
from the first device and of the sequence in which the buffer
registers were loaded; and
selection means (40, 34, 240, 234) responsive to signals
outputted from said storing means and to the signals
representative of the values generated by the counting means
2
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Last modified: November 3, 2007