Appeal No. 94-3022
Application 07/855,490
The invention relates to the construction of an integrated
circuit device which prevents a charge build-up on the surface of
the passivating layer and the formation of a parasitic MOS-
transistor by providing a conductor on the passivating layer and
biasing the conductor at a potential different from that of the
substrate.
Independent claim 1 is reproduced as follows:
1. A high voltage integrated circuit comprising:
a substrate biased at a first potential; and
interconnecting metal conductors biased at a
second potential different from said first
potential disposed on said substrate and partially
covered by a passivating layer so as to prevent
activation of parasitic MOS-transistors.
Independent claim 11 is reproduced as follows:
11. A high voltage integrated circuit comprising:
a semiconductor substrate biased at a first
potential;
a metallization pattern formed on said semi-
conductor substrate and including a plurality of
narrow, elongated metal lines;
a terminal provided external to said high voltage
integrated circuit held at a second potential
different from said first potential and electri-
cally connected to at least one of said elongated
metal lines; and
a passivation layer provided over said
metallization layer and at least partially broken
up along a length of said at least one of said
2
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Last modified: November 3, 2007