Ex parte FLANNAGAN - Page 2




          Appeal No. 95-2433                                                          
          Application No. 08/076,080                                                  


          overlooked point in our decision of June 17, 1998.                          
               More particularly, appellant alleges that even if the                  
          substitutions alleged by the examiner are considered to have                
          been obvious, the resulting structure still does not teach or               
          suggest the limitations of claim 16.  In support thereof,                   
          appellant submits five figures, starting from Fig. 2 of Nagano              
          and changes one at a time, from PNP transistors substituted                 
          for NPN transistors, to reversal of power supply polarities to              
          reversal of positive and negative power supplies and, finally,              
          to a substitution of P-channel MOS transistors substituted for              
          PNP transistors, resulting in Figure 5 in the request for                   
          rehearing.  Appellant then points out that even if all of                   
          these changes were made to Nagano’s circuit, the subject                    
          matter of claim 16 is still not reached.                                    
               Specifically, appellant cites the following differences:               
               1. Transistor Q3 does not have its source coupled to                   
          terminal OUT.                                                               
               2. Transistor Q3 does not have its drain coupled to a                  
          current mirror.                                                             
               3. The circuit of Figure 5 in the request for rehearing                
          does not function as a square-law clamping circuit.                         
               4. The current IO in resulting Figure 5 is completely                  

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