Appeal No. 95-4531
Application No. 07/939,892
connected in series between a fixed voltage and ground.
Appellants also argue (Brief, page 7) that:
Secondly, the diode means in the proposed
combinations can’t be connected between the input and
output nodes of the circuit with a “first level binary
pulse signal connected to the diode means at said input
node” and having a “second voltage level pulse signal
appearing at said output node” as claimed in paragraph
4 of claim 1. As pointed out previously, one terminal
of the two terminal diode means of both proposed
combinations is connected to a fixed potential. With
one of two terminals fixed, it is impossible to provide
a binary input pulse at one of the terminals and obtain
a binary output pulse on the other of the two
terminals.
We agree with appellants. The obviousness rejection of claims 1,
2, 4, 5, 8, 9, 16 through 24 and 26 is reversed.
The examiner recognizes (Answer, page 4) that Sedra’s
emitter follower circuit (Figure 8.41) has collector and emitter
terminals “connected directly opposite to the collector and
emitter terminals” in claim 6, but nevertheless concludes that
“[i]t would have been obvious to one of ordinary skill in the
art, at the time of the invention, to have switched the
connections of Sedra et al.’s transistors for the purpose of
utilizing the inherent larger collector-base capacitance of Sedra
et al.’s circuit as described by Eden on page 2, lines 52-55.”
Appellants argue (Brief, page 8) that:
The emitter follower of Figure 8.41 does not show as
claimed in claim 6: a) “an emitter connected to a
4
Page: Previous 1 2 3 4 5 6 7 8 9 Next
Last modified: November 3, 2007