Appeal No. 96-1246 Application No. 08/205,812 information . . . including means for mathematically applying said coefficients to said first and second sets of digital signals in parallel with said means for receiving filter coefficients" as recited in Appellants' claim 1. Furthermore, we fail to find that Fukuda teaches a "one multiplication and one logic processing means . . . , said processing means overlapping instruction processing for said two or more channels of digital signals" as recited in Appellants' claim 12. In regard to the rejection of claims 17 through 20 as being anticipated by Sakamoto, Appellants argue on pages 13 through 15 of the brief that Sakamoto fails to teach all of the claimed limitations. In particular, Appellants argue that Sakamoto does not teach or suggest executing a multiplication while loading another filter coefficient in the same processor cycle. Upon a careful review of Sakamoto, we fail to find that Sakamoto teaches the method step of "multiplying two values selected from said filter coefficients, said digital signals or an intermediate result in said processor means which in the same processor cycle loading another filter coefficient or 11Page: Previous 1 2 3 4 5 6 7 8 9 10 11 12 13 14 NextLast modified: November 3, 2007