Appeal No. 96-1621
Application No. 08/194,899
precluding storing the predecode information with all three
instructions, which certainly includes two instructions.
Since Blaner also discloses storing the instructions in pairs
(e.g., column 5, line 45), it is clear that two instructions
are stored as a “double word,” as claimed. Note, again,
contrary to appellants’ apparent intention, the claims do not
require providing predecode information for three instructions
while generating a set of predecode bits which is stored with
only two of the instructions.
We also do not agree with appellants that Blaner does not
use predecode bits to steer instructions. The penultimate
sentence of Blaner’s abstract appears to indicate that this is
precisely what Blaner is doing:
At instruction issue time, the tag fields of the
instructions are examined and those tagged for
parallel processing are sent to different ones of
the functional units in accordance with the codings
of their operation code fields.
In accordance with appellants’ grouping of the claims,
claims 20 and 23 fall with claim 19.
Turning to claim 22, this claim sets forth six generated
predecode bits, each bit indicating bundling of different
6
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