Appeal No. 97-2053
Application 08/229,624
single new ground of rejection of claims 1, 15 and 17. Claims
2-14, 16 and 18-27 were indicated as now containing
allowable subject matter. Accordingly, this appeal is now
directed to the rejection of claims 1, 15 and 17.
The disclosed invention pertains to a computing method
and apparatus for computing a cost factor associated with the
placement of cells on an integrated circuit chip.
Representative claim 1 is reproduced as follows:
1. A computing apparatus for computing a cost factor of
a placement of cells on an integrated circuit chip and
interconnect nets for said placement, comprising:
a bounder for constructing bounding boxes around said
interconnect nets respectively; and
a processor for computing overlap of said bounding boxes
and computing said cost factor as a first predetermined
function of said overlap.
The examiner cites the following references:
Antreich et al. (Antreich) 5,267,176 Nov. 30, 1993
Kim 5,398,195 Mar. 14, 1995
(filed Feb. 21, 1992)
Noble 5,392,222 Feb. 21, 1995
(filed Dec. 30, 1991)
2
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