Appeal No. 95-3920
Application No. 08/151,938
The invention is directed to a variable frequency clock
for an electronic system. More particularly, the frequency of
a system clock is reduced when a microprocessor has been idle
for a predetermined time in order to decrease power
dissipation.
Representative independent method claim 8 is reproduced
as follows:
8. A method of reducing power dissipated by an
electronic system, comprising the steps of:
monitoring a component of said system for a change in an
output thereof from a logic “1" to logic “0" or vice versa;
and
reducing the frequency of a clock of said system when
said output is constant for a predetermined interval of time.
The examiner relies on the following references:
Carter et al. (Carter) 4,980,836 Dec. 25,
1990
Watts, Jr. et al. (Watts) 5,218,704 Jun. 8,
1993
Claims 1, 3 and 8 through 10 stand rejected under 35
U.S.C. 102(e) as anticipated by Watts. Additionally, claims 1
through 11 stand rejected under 35 U.S.C. 103 as unpatentable
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