Ex parte SHIMODA - Page 2




          Appeal No. 1996-2578                                                        
          Application 08/216,807                                                      


          and 14.  Claims 8, 10, 11 and 13 have been objected to.                     


          The disclosed invention pertains to an electrical delay                     
          circuit capable of being formed entirely in a single                        
          integrated circuit.  The invention is generally used for                    
          providing a supply line delay of a predetermined time period                
          after application of a supply voltage to an input.  The                     
          invention may also be used, for example, for delaying a                     
          standard clock signal.  In conventional delay circuits, a                   
          resistor on the order of several hundred megohms and a                      
          capacitor of several microfarads are needed to generate a                   
          delay as small as several hundred milliseconds.  It is,                     
          however, impossible to commonly integrate such a large                      
          resistance and capacitance in a single monolithic integrated                
          circuit.  The inventive design accomplishes the same result by              
          utilizing components of smaller size in a manner that these                 
          components can be easily incorporated in a monolithic                       
          integrated circuit.  The invention is further illustrated by                
          the following claim.                                                        
               Representative claim 1 is reproduced as follows:                       


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