Appeal No. 96-2614
Application 08/098,740
5. An integrated capacitance multiplier circuit
comprising:
a capacitor having a first terminal connected
to a lower common voltage, and also having a second
terminal;
an operational amplifier having an output
connected to an inverting input thereof, and having
a non-inverting input connected to said second
terminal of said capacitor;
a biasing circuit with at least two separate
bias voltage outputs;
first and second field effect transistors having
respective source regions thereof electrically
connected together, and having respective gates
connected to said bias voltage outputs of said
biasing circuit;
said first transistor having a drain region
connected to said second terminal of said capacitor,
and
said second transistor having a drain region
connected to said output of said operational
amplifier; and
a multiplied-capacitance connection at said
sources of said transistors; whereby said
multiplied-capacitance connection provides an
effective capacitance to said common voltage which
is a multiple of the physical capacitance of said
capacitor, multiplied in an amount which depends on
the ratio of the conductances of said transistors.
17. A method for temperature compensating an
integrated RC circuit which comprises an integrated
resistor, an integrated capacitor and an integrated
capacitance multiplier circuit capable of virtually
multiplying the capacitance of said integrated
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