Appeal No. 1996-3365
Application 08/258,357
teachings of Callison and Hillis would
arrive at the system architecture taught by
the appellant. The same plurality of
inputs applied to a parity generation
circuit would be inputted to a first
plurality of multiplexers via a first
plurality of busses because the parity
generation circuit is used to check the
data it should be connected to an
input/output for checking and determining
the data is correct after the read/write
operation. (Emphasis added.) (Answer-page
8.)
We fail to see, in the Examiner’s explanation supra,
the claimed structure of the same plurality of inputs applied
to the parity generation circuit being inputted to the first
plurality of multiplexers via the first plurality of busses,
or how it would be obvious to create such a structure. The
Examiner’s explanation of what would or should be done is
recited in generalities which do not meet the structural
limitations claimed.
The Federal Circuit states that "[t]he mere fact
that the prior art may be modified in the manner suggested by
the Examiner does not make the modification obvious unless the
prior art suggested the desirability of the modification." In
re Fritch, 972 F.2d 1260, 1266 n.14, 23 USPQ2d 1780, 1783-84
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