Appeal No. 96-4088
Application 08/317,411
Neither reference teaches enabling a processing
element to generate parity for a first data message being sent
for that
processing element while simultaneously checking parity of a
second message being received by that processing element as
recited in Appellant's claim 1. Upon a review of Sze, we find
that Sze fails to teach enabling a processing element to
generate parity for a first data message while simultaneously
checking parity of a second message. Furthermore, we fail to
find that Chin teaches this element as well. We agree with
the Examiner that Chin teaches two sets of control signals
being transferred in opposite directions across a data
transmission interface in a first data transfer period, during
which their joint parity is determined and latched on each
side of the interface, and the results of one latched joint
parity termination is transmitted across the interface.
However, we fail to find Chin's teaching of enabling a
processing element to generate parity for a data message while
simultaneously checking parity of a second data message. In
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