Ex parte ERDELYI et al. - Page 2




          Appeal No. 97-0951                                                          
          Application 08/148,452                                                      

               This is a decision on appeal under 35 U.S.C. § 134 from                
          the final rejection of claims 1-24.                                         
               We reverse.                                                            
                                    BACKGROUND                                        
               The disclosed invention is directed to a slew rate                     
          control circuit for controlling current turn-on or turn-off                 
          rates, i.e., the "slew rates," and a voltage regulator for                  
          providing dual reference voltages to the slew rate control                  
          circuit.                                                                    
               Claim 1 is reproduced below.                                           
                    1.  A slew rate control circuit comprising:                       
                    a pair of inverter circuits;                                      
                    each of said inverter circuits comprising first                   
               and second transistors and being coupled between                       
               current limiting transistors;                                          
                    an output current switch comprising a pair of                     
               switching transistors, each pair of said switching                     
               transistors being coupled through a respective node to                 
               a respective one of said inverter circuits; and                        
                    means, including a current regulator circuit, for                 
               providing a set of current levels in the inverter                      
               circuits to define the current available for charging                  
               and discharging the capacitance on each respective                     
               node.                                                                  




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