Appeal No. 97-0984
Application 08/546,345
an inverter receiving an input signal from said reference
node, said inverter having a threshold voltage sufficiently
higher than a residual voltage to which said reference node
discharge when said supply voltage is not above said first
predetermined level that said residual voltage at said
reference node will cause said inverter to provide a logical
1 output signal;
said inverter comprising:
a PMOS transistor, a first NMOS transistor, and a second
NMOS transistor connected in series, said PMOS transistor
connected to said supply voltage and said second NMOS
transistor connected to said ground voltage, and
means for turning on said second NMOS transistor.
The examiner relied on the following references in
the
final rejection:
Mahabadi 4,885,476 Dec. 05,
1989
Shay 5,323,067 June 21,
1994
(filed Apr. 14,
1993)
Crafts 5,444,401 Aug. 22,
1995
(effectively filed Dec. 28,
1992)
The examiner cited the following additional
references in the examiner’s answer:
4
Page: Previous 1 2 3 4 5 6 7 8 9 10 11 Next
Last modified: November 3, 2007