Appeal No. 1997-1060
Application No. 08/172,848
reasonable interpretation consistent with appellant’s
specification, we find that the limitation of “. . . changing
the state of at least one device output if a redundant line
has been addressed” covers any device output, even one located
within the semiconductor device that changes state as a result
of addressing a redundancy line. A close review of the
disclosure of Saito reveals that prior to addressing a
redundant line, RDE is held high for the purpose of enabling
the row decoder (32). Saito specifically teaches in column 5,
lines 49-67 and column 6, lines 11-15 that:
Upon detection of the programmed
row address signal AR, exchange
controller 46 inhibits the
selective operation of row
decoder 32 and selects the row of
redundancy memory cell array 30B
in accordance with the detected
specified row address signal.
The selecting operation of
decoder 32 is enabled during the
time period in which the control
signal RDE is set at a high level
and disabled during the time
period in which the control
signal RDE is set at a low level.
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