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Ex parte FUJII et al. - Page 2
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Board of Patent Appeals and Interferences > 1999 > Ex parte FUJII et al. - Page 2
Appeal No. 1997-1696
Application 08/180,770
through 43 and 45, all of the claims pending in the present application.
Claims 1 through 19, 29, 35 and 44 have been canceled.
The invention relates to the method of testing input circuits, such as data-in buffer circuits or
address buffers, for a semiconductor device. In particular, the method utilizes a test wherein a negative
potential is applied to the semiconductor device. The method overcomes the prior art problem of
generating minority carriers at a junction between the layer 22 and p-well region 26 as shown in figure 2
of the present application when a negative potential is applied V . On pages 8 and 9 of the
in
specification, Appellants disclose that figure 4 shows a well region 16 is supplied with a potential which
is lower and has a greater magnitude than the potential of input signal V . Appellants disclose that this
in
arrangement prevents minority carriers generated when the potential V is negative. On pages 10
in
through 12 of the specification, Appellants disclose another embodiment shown in figure 6 in which a
first power source potential V is applied to the well regions 4 and 9 and a second power source
ss
potential V is applied to a well region 14. Appellants disclose that the first power source potential Vcc ss
is ground and the second power source potential V is a potential greater than 0. Appellants disclose
cc
that under this arrangement the minority carriers generated at the junction portion between layers 4 and
6 when V is negative flow into well region 14. This overcomes the problem of the reduction to Vin ref
due to the injection of minority carriers.
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Last modified: November 3, 2007
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