Appeal No. 1997-4120 Page 10
Application No. 08/347,341
stores a bit sequence in synchronous register 5. The bit
sequence defines a processing group constituted by processors
n and n+1. Bits n and n+1 of the sequence are set to logical
"1"; the remaining bits, to logical "0". Simultaneously, a
flip-flop 7 is triggered by an active pulse on a signal line
4. Consequently, the flip-flop 7 outputs a task termination
signal set at logical "0" at its output terminal Q and a
status signal set at logical "1" at its other output terminal.
The task termination signal is coupled to the nth line of the
signal lines 8 through which it is transferred to the
synchronous circuit unit 2n+1 of the other processor 1+n. In
addition, the status signal is supplied to a TEST input
terminal of the first processor 1n. The first processor 1n
interrupts its processing until the status signal at the TEST
input terminal is set to logical "0." Col. 9, ll. 1-24.
Values stored in the synchronous register 5 and those on
the
signal lines 8 are supplied to the determination circuit 6.
When the nth and (n+1)th lines of the signal lines 8 are set
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Last modified: November 3, 2007