Ex parte GEPHARDT et al. - Page 2




              Appeal No. 1997-0416                                                                                       
              Application No. 08/125,406                                                                                 




                                                   BACKGROUND                                                            

                     The appellants' invention relates to a system and method for restarting a peripheral                
              bus clock signal and requesting mastership of a peripheral bus.  The stopping and                          
              restarting of the clock are disclosed as a power saving feature.   An understanding of the                 
              invention can be derived from a reading of exemplary claim 14, which is reproduced                         
              below.                                                                                                     
                     14.  A method for re-starting a peripheral bus clock signal and requesting                          
                     mastership of a peripheral bus comprising the steps of:                                             
                     stopping said peripheral bus clock signal upon the occurrence of a                                  
                            predetermined condition;                                                                     
                     generating an asynchronous clock request signal within an alternate bus                             
                            master;                                                                                      
                     re-starting said peripheral bus clock signal in response to said                                    
                            asynchronous clock request signal; and                                                       
                     generating a synchronous bus request signal within said alternate bus                               
                            master to request mastership of said peripheral bus after said                               
                            peripheral bus clock signal has been re-started, wherein said                                
                            synchronous bus request signal is synchronous to said peripheral bus                         
                            clock signal.                                                                                








                                                           2                                                             





Page:  Previous  1  2  3  4  5  6  7  8  9  10  Next 

Last modified: November 3, 2007