Appeal No. 1997-0586
Application No. 08/243,559
Johnson into [sic] system taught by Beckwith et al. ... by
including the prediction target address at the branch
instruction level, thereby processing the branch instruction
without waiting for a decoder or execution unit to indicate
the proper fetched action to be taken for correctly predicted
branching.”
Appellants argue [brief, page 11] that “the abstract and
disclosure of Johnson as a whole teach that the branch
prediction information of Johnson is stored in a cache block
of instruction cache memory, and not in a field of the branch
instruction. Johnson fails to disclose or suggest a branch
instruction specifying a prediction of the target address in
addition to a register specifier for the actual target
address.”
We have also reviewed appellants’ further arguments
[brief, pages 12 to 17 and reply brief, pages 2 to 4] and the
Examiner’s responses thereto [answer, pages 3 to 8 and
supplemental answer, pages 1 to 3] and are of the view that
Johnson does not provide the teaching suggested by the
Examiner. In fact, the Examiner “agrees with appellant’s
[sic, Appellants’] argument that Johnson et al [sic, et al.]
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