Ex parte BOWERS - Page 2




          Appeal No. 1997-0706                                                        
          Application No. 08/040,528                                                  

          Appellant’s filing of the Reply Brief, was also entered by the              
          Examiner.  At page 2 of the Answer, the Examiner indicted the               
          withdrawal of the rejection of claims 2-4, 8-10, 14-16, 20,                 
          and 21.  Accordingly, only the rejection of claims 1, 6, 7,                 
          12, 13, 18, and 19 is before us on appeal.                                  
               The claimed invention relates to a multiple use chip                   
          socket in which first and second types of chips can be                      
          supported in a single chip socket.  The particular type of                  
          chip installed in the  socket is determined by control logic                
          that reads a predetermined memory location of the chip.                     
          Addressing signals are selectively applied to the chip socket               
          by the control logic depending on the type of chip determined               
          to be installed in the socket.                                              
               Claim 1 is illustrative of the invention and reads as                  
          follows:                                                                    
               1. A multiple use chip socket comprising:                              
               a chip socket for receiving either a first chip type or a              
          second chip type, said first chip type having a first set of                
          signals, said second chip type having a second set of signals               
          different from said first set of signals; and                               
               control logic coupled to said chip socket for determining              
          whether a chip of said first chip type or said second chip                  
          type is installed in said chip socket by reading a                          
          predetermined memory location of a chip installed in said chip              
          socket and for providing signals to said chip socket                        
                                          2                                           





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