Appeal No. 1997-1572
Application 07/792,534
for storing vector data (RAM 5, also see column 2, line 62 to
column 3, line 8), and a memory area after the recognition is
completed (5d) [column 5, lines 45 to 48]. Therefore, we
sustain the rejection of claim 3.
Claims 7 and 16. These claims each call for the
recognition processor to be comprised of “first and second
parallel recognition processors” each operable to receive
vector stroke data from the collection processor. Appellant
argues that “Appellant has not claimed mere parallel
processing.” [Brief, page 10, see also reply brief, page 2].
We note that this is merely a conclusory statement and not a
substantive argument. Furthermore, Appellant has not shown in
the specification figures the recognition processor to be
comprised of a first and a second processors. A brief mention
of such arrangement is found on page 11 of the specification.
We agree with Appellant that the invention does not reside in
the concept of parallel processing. Therefore, we are of the
view that once Nakatsuka is recognized to have a recognition
processor, to have it replaced by two
processors acting in parallel (that is duplicated what is
11
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