Appeal No. 1997-2439
Application 08/417,701
connected to said second I/O interface circuit, wherein the second I/O bus has a
second set of fixed addresses associated with said second I/O bus, and further wherein
the first set of fixed addresses are the same as the second set of fixed addresses;
wherein said first I/O bus circuit includes (1) means for identifying memory addresses
and I/O addresses assigned to said first I/O bus by the computer system, and (2)
means for translating addresses during accesses to the first set of fixed addresses
associated with said first I/O bus from memory addresses and I/O addresses assigned
to said first I/O bus by the computer system into addresses of the first set of fixed
addresses associated with first I/O bus, and wherein said second I/O interface circuit
includes (1) means for identifying memory addresses and I/O addresses assigned to
said second I/O bus by the computer system, and (2) means for translating addresses
during accesses to the second set of fixed addresses associated with said second I/O
bus from memory addresses and I/O addresses assigned to said second I/O bus by the
computer system into addresses of the second set of fixed addresses associated with
said second I/O bus."
We note that independent claim 23 recites a method comprising the steps of:
providing a first I/O bus having a first set of fixed addresses associated therewith;
providing a second I/O bus having a second set of fixed addresses associated
therewith, wherein the first set of fixed addresses are the same as the second set of
fixed addresses . . . translating addresses during accesses to the first set of fixed
addresses associated with the first I/O bus or the second set of fixed addresses
associated with the second I/O bus from memory addresses and I/O addresses
assigned to the first I/O bus or the second I/O bus by the computer system into a
addresses of the first set of fixed addresses associated with the first I/O bus or the
second set of fixed addresses associated with the second I/O bus."
We note that independent claim 29 recites a method which has similar method steps as recited in
Appellants' claim 23.
On page 5 of the answer, the Examiner argues that Frieder's addresses of each device is
inherently the same when it is accessed via the first I/O bus as when it is accessed via the second I/O
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