Ex parte EVOY et al. - Page 2




              Appeal No. 1997-3156                                                                                       
              Application No. 08/372,423                                                                                 


                     Representative independent claim 24 is reproduced as follows:                                       
                     24.  A system comprising:                                                                           
                            an integrated circuit, the integrated circuit using a clock signal to                        
                     generate an output signal on an output pin of the integrated circuit; and,                          
                            a monitoring circuit which monitors core temperature of the integrated                       
                     circuit, the monitoring circuit comprising                                                          
                                   a phase delay detection circuit coupled to the output pin                             
                            of the integrated circuit and to the clock signal, the phase                                 
                            delay detection circuit including                                                            
                                          digital signal generating means, coupled to the output                         
                            pin of the integrated circuit, for generating a digital signal, wherein                      
                            changes in phase delay between the output signal on the output pin of                        
                            the integrated circuit and the clock signal result in changes in a duty                      
                            cycle of the digital signal generated by the digital signal generating                       
                            means, and                                                                                   
                                          integrating means, coupled to the digital signal                               
                            generating means, for integrating the digital signal to produce an                           
                            integrated signal, a voltage level of the integrated signal indicating                       
                            relative phase delay between the output signal on the output pin of the                      
                            integrated circuit and the clock signal, and                                                 
                                          control means coupled to the integrating means, for                            
                            changing an operating frequency of the integrated circuit when the                           
                            voltage level of the integrated signal indicates that the phase delay                        
                            between the output signal and the clock signal is longer than a                              
                            predetermined value.                                                                         
                     The examiner relies on the following references:                                                    
                     Swapp                       4,858,208                    Aug. 15, 1989                              



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