Ex parte ISHIDA et al. - Page 8




               Appeal No. 1997-3166                                                                                               
               Application No. 08/509,638                                                                                         


               37 CFR 1.196(b): Claim 21 is rejected under 35 U.S.C. § 103(a) as unpatentable over Oldham.                        

                      Oldham discloses a memory cell comprising a flip-flop circuit with first and second inverters;              

               see Fig. 1 and column 1, line 65 through column 2, line 20.  The first inverter has a first driver transistor      

               T1 and a first load transistor T2.  The second inverter has a second driver transistor T3 and a second             

               load transistor T4.  The circuit includes a first word transistor T5 and a second word transistor T6.  At          

               least for the reason that first and second load transistors T2, T4 are distinct and separate physical              

               structures, the “gate area” of the first is different from the “gate area” of the second.  In addition,            

               columns 3 through 5 of the written description detail forming the gate insulating layer of one load                

               transistor differently from the other, succinctly set forth by Oldham in Claims 1 and 5 as the “means for          

               selectively altering charge state.”                                                                                

                      According to appellants, Claim 21 distinguishes over Oldham because “[t]here is neither                     

               teaching nor suggestion” of the Claim 21 limitation that “‘a channel of said first load transistor is longer       

               than a channel of said second load transistor.’” (Brief, page 5.)  However, the reference details the              

               following with respect to first and second load transistors T2, T4:                                                

                              In order to insure that the memory cell (in connection with supply voltage U )                      
                                                                                                            cc                    
                      flips into a predetermined position corresponding to a continuously stored digital                          
                      information, the field effect transistors T2 and T4 are designed with different channel                     
                      resistances.  For this purpose, dimensions of their source-drain channels are embodied                      
                      differently.  If, for example, the transistor T2 has a channel width W which, with respect                  
                      to its channel length L, is in a ratio of 20:4, while the quotient of channel width to                      
                      channel length in the case of transistor T4, for example, is 15:4, then the channel                         
                      resistance of T2, because of the larger channel width, is lower than that of T4.                            

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