Appeal No. 1997-3426
Application 08/373,052
lines referred to by the Examiner at columns 199 and 207 do
not even appear to describe the functioning of the
interfaces 202 and 206. In view of the length and complexity
of the reference, we review only those portions specifically
relied on by the Examiner. We find that Douglas does not
teach or suggest the limitation that "at least one received
packet causes a portion of the other circuitry to assume
control of at least some of the data processor signal lines
for executing a function specified by the packet" (claim 12)
or "assuming control over at least some of the data processor
signal lines and reading data from a memory location that is
accessible to the data processor" (claim 28). Therefore, we
do not need to reach the issue of motivation.
The Examiner states that item 16 in Figure 1 of Underwood
includes other circuitry which is caused to assume control of
the data processor signal lines (FR3).
Appellants note that Underwood discloses a multiprocessor
system wherein one processor performs an automatic fault
isolation test (FIT) on another processor. One of the
processors is selected to be a master and the processor to be
tested is the slave. The master exercises control over the
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