Appeal No. 1997-3818
Application 08/208,517
type of memory (page 73, lines 5 to 22).
Interface circuitry (80) receives coded
information from the static decoder and
selects a protocol for information
transfer. In the preferred embodiment, the
protocol includes addressing information
having multiplexed row/column addresses for
accessing dynamic memories or un-
multiplexed addresses for accessing static
memories.
. . . .
The data processing apparatus (100) may
also control the number of bits
transferred. An external part (302)
supplies a bus size signal (BS[1:0]) to a
static decoder. The internal data bus is
coupled to an external data bus of
selectable size. The interface circuitry
selects a bus size protocol based upon the
received bus size signal (BS[1:0]). Thus
the data processing apparatus may establish
the size in bits of data transfers to
accommodate the selected bus size. An
endian mode memory store[s] an indication
of a big endian mode or a little endian
mode. The number of bits transferred is
based upon the data bus size signal
(BS[1:0]) but the identity of the data bus
lines used is based upon the current endian
mode (page 165, line 20 to page 169, line
19, Tables 24a, 24b, 25a, 25b, 26, 27, 28
and 29). [Brief at 2-3.]
B. The claims
3
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