Appeal No. 1997-4463
Application 07/988,712
However, that some reason can be invented is not evidence of
obviousness in the prior art. Central storage of messages is
contrary to the teachings of Bullock. It appears that the
motivation for the proposed modification comes from
Appellant's disclosure.
In addition, Pfeiffer does not disclose outputting
information from a processor at a rate that corresponds to the
utilization rate at a certain location. Pfeiffer merely
states that the bus bit rate must equal the clock speed of the
controller (col. 11, lines 66-68). We agree with Appellant
that this implies the data rates for a transmitter and a
receiver must be matched, which has nothing to do with reading
a message (or other kind of information) out of storage at a
rate corresponding to the utilization rate somewhere else.
In summary, the combination of Bullock and Pfeiffer does
not teach or suggest: (1) "means responsive to the operation
of the input device for one of said sites for initiating the
reading out of a message to be provided at the site from the
means for addressably storing [at the common source]," and
(2) "the reading out of a message for each site . . .
proceeding concurrently for all sites at a rate for each site
- 13 -
Page: Previous 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Next
Last modified: November 3, 2007