Appeal No. 1998-0069
Application 08/356,946
DECISION ON APPEAL
This is a decision on appeal under 35 U.S.C. § 134 from
the final rejection of claims 1-17.
We reverse.
BACKGROUND
The disclosed invention is directed to a device and
method for testing an interconnection between integrated
circuits (ICs) having inputs with fixed logic values on a
printed circuit board. Logic circuits utilize ICs which
increasingly include Boundary Scan Test (BST) logic. These
ICs enable testing of the interconnection function of the
printed circuit board support in conformance with the BST
method. IC inputs which are to receive a fixed logic value
are usually provided with so-called pull-up or pull-down
resistors, such as resistor 26 and resistors 22 in figure 1
to provide a logic "1" and logic "0," respectively. Special
test points on the conductor and the resistor are required
to test the interconnection to the IC. The interconnection
between the input to a pull-up or pull-down resistor cannot
be tested by the BST method because resistors do not
comprise test logic. The invention provides fixed logic
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