Ex parte SEZNEC - Page 1





               The opinion in support of the decision being entered                   
          today was not written for publication and is not binding                    
          precedent of the Board.                                                     
                                                                 Paper No. 24         
                       UNITED STATES PATENT AND TRADEMARK OFFICE                      
                                     ____________                                     
                          BEFORE THE BOARD OF PATENT APPEALS                          
                                   AND INTERFERENCES                                  
                                     ____________                                     
                                Ex parte ANDRE’ SEZNEC                                
                                     ____________                                     
                                 Appeal No. 1998-1506                                 
                              Application No. 08/302,695                              
                                     ____________                                     
                               HEARD: November 14, 2000                               
                                     ____________                                     
          Before RUGGIERO, DIXON, and GROSS, Administrative Patent Judges.            
          GROSS, Administrative Patent Judge.                                         



                                  DECISION ON APPEAL                                  
               This is a decision on appeal from the examiner's final                 
          rejection of claims 1 through 5, which are all of the claims                
          pending in this application.                                                
               Appellant's invention relates to a cache memory device.                
          Claim 1 is illustrative of the claimed invention, and it reads              
          as follows:                                                                 
               1.   An improved cache memory device for use in a data                 
          processing system which includes an addressable main memory                 
          (MP); at least one request input/output (ESRQ) for receiving a              
          request (REQ) for access to a data item stored in the                       





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