Ex parte HARDEE - Page 11




          Appeal No. 1998-1657                                      Page 11           
          Application No. 08/674,282                                                  


                    Young shows all the limitations of the claimed                    
               sense amplifier arrangement in figs.l-4, comprising                    
               a sense amplifier latch circuit 21a-24b and a local                    
               column read amplifier 28,25,27,YDR,S, S, in each                       
               sense amplifier circuit, except the use of first and                   
               second local sense amplifier drive transistors, as                     
               recited in claims 5,25,33 and 35.                                      
                    However, EP (`880) shows a plurality of sense                     
               amplifier 57 each comprising a latch circuit 51-56                     
               and first and second local sense amplifier drive                       
               transistors 58 and 61 in figs 1-13.                                    
          (Final Rejection at 3.)  The appellants argue, "21a-24b of                  
          Young form a memory cell latch and not a sense amplifier                    
          latch, and 25, 27, 28 form a column sense amplifier and not a               
          sense amplifier latch."  (Reply Br. at 5.)  They further                    
          argue, "25, 27, 28 is a column sense amplifier, not a read                  
          amplifier."  (Id. at 11.)                                                   


               Claim 5-7 and 20-24 specify in pertinent part the                      
          following limitations:                                                      
                    a plurality of column read amplifiers                             
               corresponding to said plurality of sense amplifiers;                   
               and                                                                    
                    a plurality of data read lines;                                   
                    each said column read amplifier being                             
               responsively coupled to at least one of said                           
               internal nodes of the latch circuit of the                             
               corresponding sense amplifier, each said column read                   
               amplifier being coupled to at least one said data                      
               read line.                                                             








Page:  Previous  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  Next 

Last modified: November 3, 2007