Ex parte CHAN et al. - Page 14




          Appeal No. 1998-2661                                                        
          Application 08/633,267                                                      

          weighed within 35 U.S.C. § 103, the artisan would not have                  
          considered this reference to teach away from the claimed                    
          invention to the extent we relied upon it.                                  
               Finally, we turn to the examiner's last stated rejection               
          of all claims on appeal, claims 1 through 16, 18 and 19 as                  
          being obvious over the collective teachings and showings of                 
          Sato and Deosaran.  We sustain this rejection only as to claim              
          1.                                                                          
               It appears that the examiner relies upon Sato only for                 
          those claims that specifically recite virtual rename buffers,               
          and these include all claims on appeal except for claim 1.                  
          The examiner apparently sees some correspondence between the                
          virtual registers associated with the pseudo-codes associated               
          with source program instructions during a compiling operation               
          and their relationship to corresponding real registers                      
          associated with finally converted machine codes.  However, we               
          are in agreement with appellants' views expressed at page 15                
          of the principal brief on appeal:                                           
                    Sato is not relevant prior art to the                             
                    present invention, since Sato teaches a process                   
                    implemented within a compiler, and does not                       
                    address the actual execution of instructions in                   
                    parallel pipelines.  As can be seen by noting                     
                    Figure 3, step S10 converts the pseudo-code into                  
                                         14                                           





Page:  Previous  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  Next 

Last modified: November 3, 2007