Appeal No. 1998-1800
Application No. 08/430,453
regardless of whether the address being operated upon is
designated as cache inhibited. Read operations, on the other
hand, are performed in a conventional manner in which
addresses indicated as noncacheable are not allocated in the
cache. Appellants assert at pages 3 and 4 of the
specification that this technique permits the cache memory to
remain coherent with the main memory even for memory ranges
designated as cache inhibited, thereby eliminating the need
for flushing the cache when memory areas are redesignated from
noncacheable to cacheable.
Claim 1 is illustrative of the invention and reads as
follows:
1. A method for managing a cache memory during a memory
operation comprising the steps of:
receiving an address at a cache controller;
determining whether said address has been designated
as noncacheable;
if said address has been designated as noncacheable
and said memory operation is a read operation, then accessing
a main memory to retrieve therefrom; and
if said address has been designated as noncacheable
and said memory operation is a write operation, then accessing
said main memory and updating said cache memory.
2
Page: Previous 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Next
Last modified: November 3, 2007