Appeal No. 1998-2513
Application No. 08/171,427
speed instruction generator is a voltage controlled oscillator. We agree that the
evidentiary basis for the rejection of those claims is lacking. The allocation of burdens
requires that the USPTO produce the factual basis for its rejection of an application under
35 U.S.C. § § 102 and 103. In re Piasecki, 745 F.2d 1468, 1472, 223 USPQ 785, 788
(Fed. Cir. 1984) (citing In re Warner, 379 F.2d 1011, 1016, 154 USPQ 173, 177 (CCPA
1967)). The one who bears the initial burden of presenting a prima facie case of
unpatentability is the examiner. In re Oetiker, 977 F.2d 1443, 1445, 24 USPQ2d 1443,
1444 (Fed. Cir. 1992).
The statement of the rejection (Answer, page 4, final paragraph) appears to be
based on appellant’s own teachings in the specification. The examiner’s further
commentary (Answer, page 7) does not refer to any evidence in the record. Alleging that
voltage controlled oscillators were “notoriously well known in the art” does not speak to the
subject matter as a whole of claims 9 and 14.
Taneka discloses in Figure 5, element 5, an “F/V” (frequency to voltage) converter.
We may conclude that the reverse operation -- voltage to frequency conversion -- was
routine in the art. However, as appellant points out, there are no teachings in the evidence
upon which the rejection is based to establish that a voltage controlled oscillator was the
particular hardware suggested as the capstan speed instruction generator. Since a prima
facie case of obviousness has not been established for those claims, we do not sustain
the rejection of claims 9 and 14.
-9-
Page: Previous 1 2 3 4 5 6 7 8 9 10 11 Next
Last modified: November 3, 2007