Appeal No. 1999-0011
Application No. 08/428,812
The invention is related to an improved multi-bit error
correction system. The inventive error correction system
performs a fast error correcting operation on individual bits
within multi-bit modules. In the specific implementation, the
invention uses Hamming code decoders, m modules for a n x m
bit data word, with each module having m bits. The error bits
of each module are combined to form a set of parity bits.
Syndrome bits are generated from the parity bits and used to
locate errors in the bits. Finally, errors in the bits are
corrected in a conventional manner to provide corrected data
bits. Thus, the invention provides a high speed error
detection and correction technique for data containing multi-
bit words.
The invention is further illustrative by the following
claim.
Claim 1. An improved multi-bit error correction system
comprising:
first means for providing an n times m bit data word and
second means for correcting multiple bits in said data
word[,] said second means including m parallel one bit Hamming
code decoders.
The examiner relies on the following references:
2
Page: Previous 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Next
Last modified: November 3, 2007