Appeal No. 1999-0168
Application No. 08/540,349
system. More particularly, the system utilizes a core central
processing unit for instruction execution and a coprocessor
for system control and exception processing. Upon
notification of an exception, the normal sequence of
instruction processing by the core central processing unit is
suspended and an exception program counter is loaded with a
restart location for use after the exception is serviced.
Appellants indicate at pages 1 and 2 of the specification that
after the context of the current operating state of the core
central processing unit is saved, the coprocessor is enabled
to service the exception by loading a status register with
operating mode and interrupt enabling bits, thereby relieving
the core central processing unit of the burden of servicing
exceptions.
Claim 1 is illustrative of the invention and reads as
follows:
1. A method of handling exceptions in a microprocessor
system having a core central processing unit (CPU) and a
coprocessor for system control comprising the steps of:
a) suspending a normal sequence of instruction by said
CPU,
b) loading an exception program counter with a restart
location for use after the exception is serviced,
2
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