Appeal No. 1999-0568
Application No. 08/447,594
Appellants argue that the queuing scheme of Barajas
relates to storing invalidation address signals in an
invalidation queue. Appellants argue that invalidation
address signals are not the same as unwritten write
request data signals as recited in claim 1 so that the
combined teachings of the applied prior art do not teach
or suggest the invention as claimed (brief, pages 17-20).
The examiner responds that Barajas is directed to an
adjustable cache writing policy which has the claimed
steps (answer, page 6). Appellants respond that the
invalidation address signals of Barajas are not the same
as the unwritten write request data signals of claim 1 so
that the steps of claim 1 which recite operations
specifically performed based on unwritten write request
data cannot be met by the operation in Barajas of queuing
invalidation address signals (reply brief, pages 4-5).
We agree with the position argued by appellants.
More specifically, we essentially agree with appellants
that the queued invalidation address signals of Barajas
are not the same as write request data stored in a cache
memory. The steps of initiating and terminating in claim
10
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