Appeal No. 1999-0874
Application 08/726,733
Treating independent claim 7 first, the claimed first conductive layer comprises
gate electrode 4. The conductive region claimed corresponds to the diffused drain
regions 6, 8. The first insulation layer comprises silicon oxide layer 9 on top of which is
silicon nitride layer 10. The diameter of the first hole comprises the width extending
between the diffused regions 6 just above the diffused region 8.
The claimed second insulation layer comprises silicon oxide layer 11. At this
level of the vertically integrated structure of Figures 38 and 39, it is seen that the hole
110 has a larger diameter as claimed than the one just described with respect to the
surface diffused regions 6, 8 corresponding to the first hole, thus meeting also the
recitation of claim 7 that the second hole be larger than the first hole.
The use of sidewall oxides in vertical integration techniques for integrated circuits
is detailed in Teng to aid in patterning contact holes, which techniques are directly
applicable to the hole diameters and the function of the chip surface contact to the
claimed second conductive layers of polysilicon 17 and tungsten silicide 18 in prior art
Figures 38 and 39. The problems associated with the formation of the prior art
structures between Figures 38 and 39 of the appellants’ admitted prior art involve the
desirability of placing circuit elements such as the gate electrodes 4 in Figure 36 closer
together in Figure 37 compared to Figure 36, thus increasing the integrated circuit
density of active circuit elements. This same consideration drives the disclosure in
Teng from the initial paragraphs at column 1 of this reference.
7
Page: Previous 1 2 3 4 5 6 7 8 9 10 11 12 13 Next
Last modified: November 3, 2007