Appeal No. 1999-1455
Application 08/753,556
a different length. The corresponding discussion of Figure 2 at the bottom of page 3 of the
specification states that this figure “illustrates a refinement which can be used when at
least one of the transistors can be divided into two or more narrower transistor segments
connected in parallel.” This language is the basis of the recitation at the top of page 4 that
the Figure 3 embodiment alters both width and lengths of each segment. The abstract at
specification page 7, lines 8 through 10 thereof indicates that the transistor is “formed as
two or more sub-transistors.” Originally filed claims 2 through 4 indicate that the transistor
of claim 1 is “formed from a plurality of parallel connected sub-transistors.”
On the other hand, the examiner instituted the present rejection under 35 U.S.C.
103 in the final rejection on the basis of newly applied art for new claims presented after
claims 1 through 6 had been canceled. Note the art rejection set forth in a simple form at
the bottom of page 2 of the final rejection. The advisory action issued by the examiner on
June 16, 1998 in response to appellants’ Response to the Final Rejection filed on June 1,
1998, states that with respect to this Request for Reconsideration of the final rejection “the
claims do not require segments connected ‘in parallel,’ they require ‘parallel segments,’
which is taught by Okuzumi.”
The focus of the arguments presented by appellants in the brief and reply brief as to
the issue under 35 U.S.C. § 103 emphasizes that the Figure 3 embodiment is intended to
be claimed and “in which both the lengths and widths of each of the parallel connected
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