Appeal No. 1999-1855
Application 08/738,916
skilled in the art would interpret this to state (i.e.,
anticipate) that the circuit of Fig. 3 can be such a structure
[p-substrate with n-wells], while, it is preferred that [it]
is not" (EA8). The Examiner finds that "even if S8 is an
'n-channel' as stated in line 24 of page 3 [of specification],
it is clear that the circuit will still operate" (EA8).
Unfortunately, Appellant's reply brief does not address
these reasons. The Examiner's finding that the description of
figure 3 teaches that it is possible, just not preferable or
conventional, to implement the conventional negative voltage
generator in a p-substrate with an n-well CMOS process instead
of with a p-well CMOS process seems reasonable. We are not
inclined to reverse the Examiner's finding absent some
argument by Appellant why the Examiner errs or why the
specification should be interpreted in another way. Appellant
has also not responded to the Examiner's finding that the
circuit would work if S8 was an n-channel transistor in a
grounded p-substrate. The specification states that it is an
"object to provide a negative voltage generator using N-well
CMOS technology which can generate a voltage more negative
than a parasitic diode voltage drop" (specification, p. 4,
- 10 -
Page: Previous 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Next
Last modified: November 3, 2007