Appeal No. 1999-2000
Application 08/859,494
202. Therefore, we find that Appellants’ admitted prior art
figure 7 does not teach or suggest a non-transparent electrode
completely overlapping the channel region.
Asano discloses on page 2, lines 44 through 65, an EPROM
having an electric conducting layer 70 partially covering gate
oxide film 63 and polycrystalline silicon gate film 40.
However, Asano does not teach a non-transparent electrode
completely overlapping the channel region as recited in
Appellants’ claim 44.
Fisher teaches in column 5, lines 52 through 59, that an
insulation layer 96 blocks the light to the semiconductor
deposit 94. However, Fisher does not teach that the non-
transparent electrode is connected to the drain region in
order to completely overlap the channel region. Therefore, we
fail to find that the applied references teach Appellants’
claim limitation of providing, “a non-transparent electrode
connected to the drain region, the non-transparent electrode
completely overlapping the channel region” as recited in
Appellants’ claim 44.
The Federal Circuit states that “[t]he mere fact that the
6
Page: Previous 1 2 3 4 5 6 7 8 9 10 Next
Last modified: November 3, 2007