Appeal No. 1999-2688
Application No. 08/751,057
signals. In particular, a processor connected to the IQ
output of the demodulator determines an associated IQ value
address in a data memory for each IQ value and a respective
frequency is stored under each address of the data memory,
wherein the respective frequency is a frequency with which a
respective address, thereby the corresponding IQ value, has
been determined in a predetermined acquisition time. That is,
each address has stored thereunder, the number of times a
signal status occurs within a predetermined acquisition time.
The predetermined acquisition time is set by a control switch.
If the processor determines, within the predetermined time
span, that an IQ value is allocated to an address of the data
memory, and thereby to a respective pixel position, the
processor increases the content of that data memory address by
one. In this manner, under each address of the data memory is
stored the frequency with which this address, and thereby the
associated pixel, respectively occurs.
Representative independent claim 1 is reproduced as
follows:
2
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