Appeal No. 1999-2747
Application 08/757,979
for controlling the operation of a storage array after a
failure in the storage array (specification, page 4, lines 2-
6). Cache memory array (specification, page 6, lines 30-31;
figure 2, numeral 20) includes a tag array (figure 2, numeral
30) and a data array (figure 2, numeral 50). An address
(figure 2, numeral 22), including a tag portion (figure 2,
numeral 24) and an index portion (figure 2, numeral 26), is
presented to the cache array for selection of a cache line
for storage or retrieval of data in the data array
(specification, page 6, line 31, through page 7, line 5).
The tag bit outputs from the address are connected to
respective inputs of a comparator (figure 2, numeral 28)
wherein address information from the tag array is compared
with the tag portion of the address (specification, page 7,
lines 5-8). Each line in the tag array includes set fields
(figure 2, numeral 34) which include a tag portion (figure 2,
numeral 36), a MESI field (figure 2, numeral 38) and a least
recently used field (figure 2, numeral 40) (specification,
page 7, lines 12-15). The tag field for the selected line is
output to the comparator for comparison with the tag portion
of the input address to determine if there is a match between
2
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