Appeal No. 1998-2578
Application No. 08/443,307
stored in an arrangement that is “capable of” constructing multiple screens. The image
memory in Kashigi is not only “capable of,” but does, store multiple screens in the same
sense as Appellant’s display memory 20 stores multiple screens.
Memory 80, as shown in Figure 5, is a four-line (four horizontal scanning lines)
buffer memory, comprised of four one-line memories 91, 92, 93, and 94 (Fig. 4). See
Kashigi at col. 6, ll. 22-28; col. 7, ll. 16-24. The “one-frame memory and read-side
device” 73 shown in Figure 5 is more fully described in the disclosure of the Figure 3
embodiment, and with circuit details shown in Figure 3. The device contains a one-
frame memory 30 which, in the Figure 3 embodiment, is filled with image data in a
sequence controlled by selector device 76. Splitting first and second input television
signals along a vertical line of each picture, and combining the split pictures into a
composed picture, is described at the paragraph bridging columns 6 and 7.
The Figure 5 embodiment uses selector device 136 for filling one-frame
memory 30, contained within device 73. As further described at column 11, lines 3
through 34 of Kashigi, one-frame memory 30 is filled with digital image data comprised
of pulse code modulated data codes 88, which are multiplexed through contacts A, B,
C, and D. The one-frame memory 30 is thus filled in a piecemeal fashion from smaller
memory 80 contained in each of the “write-side” devices 131, 132, 133, and 134, each
of the “write-side” devices corresponding to a separate input (11, 12, 128, 129) to the
system.
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