Appeal No. 1999-1449
Application 08/640,351
sample value (Yk +t) and an estimated ideal sample value (~Yk +t),
and the step of synchronizing the error value, ek, to the
asynchronous sample values (Xk) (25). See figures 8B, 8C,
specification, page 36, lines 4-10. Additionally, the claimed
method comprises the step of interpolating the equalized sample
values (32) to generate baud rate synchronous sample values
(B102). See figures 8B, 8C, and specification, page 36, lines
10-18. Last, the method comprises the step of detecting digital
data from the baud rate synchronous to the sample values (Xk)
(25). See figure 3, and specification, page 17, lines 24 through
page 18, line 1. Thus, Appellants’ claim 17 requires method
steps performed by the interpolation circuit (C106) to
synchronize the error values e(k) to the channel sample values
X(k) (25), the claimed asynchronous sample values. Therefore, we
will not sustain the Examiner’s rejection of claims 17 and 18 for
the same reasons discussed above.
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